As the operational frequency and integration increases, the overall performance of electronic systems becomes increasingly sensitive to the capacitive, inductive and resistive characteristics of the ICs associated therewith, as well as the structures employed to interconnect the ICs. The aforementioned characteristics result in unwanted currents propagating along either a DC power trace or a signal trace that degrade the operation of the ICs. For example, during operation, the amount of current demand of an IC, such as a processor, can vary rapidly between milliamps to tens of amps. This may produce voltage spike in the power plane through which current is supplied to the IC. The magnitude of spikes are proportional to the frequency of operation of the IC. This produces a voltage drop across the inductance associated with the power planes in direct proportion to the rate of change of current. The voltage drop may substantially reduce the operational frequency of the IC. Prior art techniques to solve this problem include use of off-chip de-coupling capacitors distributed throughout the power plane on the printed circuit board to which the integrated circuit is mounted. However, the frequency of operation of the off-chip de-coupling capacitors were limited.
U.S. Pat. No. 5,973,910 to Gardner discloses a de-coupling capacitor that attempts to overcome the problems associated with off-chip de-coupling capacitors. Specifically, Gardner discloses reducing noise associated with current propagating along a DC power line embedded in an IC by connecting a de-coupling capacitor as close to a load as possible. To that end, Gardner discloses a de-coupling capacitor incorporated into an integrated circuit. The capacitor is disposed over a first region of a substrate comprising electronic circuitry, and not over a second region of the substrate. The capacitor comprises a lower and an upper conductive layer separated by an interposing insulative layer. An additional insulative layer is disposed beneath the lower conductive layer while another insulative layer is disposed above the upper conductive layer.
U.S. Pat. No. 5,872,697 to Christensen et al. discloses an integrated circuit having a de-coupling capacitor integrally formed therewith. The capacitor includes a dielectric film disposed over a final metal layer of the integrated circuit. A conductive film is disposed over the dielectric layer to provide capacitance in the dielectric layer. In this manner, the performance of the integrated circuit is described as being enhanced. Specifically, the performance is enhanced by facilitating higher switching speeds due to the faster response of the capacitor to power supply bounce resulting from large currents produced by the high speed switching. A drawback with the prior art techniques for reducing surge currents is that they typically require greatly increasing the area required to manufacture an integrated circuit due to the formation of the de-coupling capacitor or necessitate a limit in the operational frequency of the integrated circuit.
What is needed, therefore, is a technique for reducing surge currents without increasing the area required to form the integrated circuit or reducing the operational frequency of the same.